Dr. Aviral Shrivastava is Associate Professor in the School of Computing Informatics and Decision Systems Engineering at the Arizona State University, where he has established and heads the Compiler and Microarchitecture Labs (CML) (http://aviral.lab.asu.edu/). He received his Ph.D. and Masters in Information and Computer Science from University of California, Irvine, and bachelors in Computer Science and Engineering from Indian Institute of Technology, Delhi. He is a 2011 NSF CAREER Award Recipient, and recipient of 2012 Outstanding Junior Researcher in CSE at ASU. His 2 students have received the outstanding MS thesis award in CSE at ASU. His papers have been the best paper candidate at DAC 2017, ASPDAC 2008, and won the best student paper award at VLSI 2016. His research lies at the intersection of compilers and architectures of embedded and multi-core systems, with the goal of improving power, predictability, performance, temperature, energy, reliability and robustness. NSF and several industries including Microsoft, Raytheon Missile Systems, Intel, Nvidia, etc fund his research. He serves on organizing and program committees of several premier embedded system conferences, including DAC, ICCAD, ISLPED, CODES+ISSS, EMSOFT, CASES and LCTES, and regularly serves on NSF and DOE review panels.
Title of Talk: Time in Cyber-Physical Systems
Abstract: Cyber-Physical systems are those that tightly integrate physical and computational systems. One of the big challenges in distributed cyber-physical systems is establishing a common notion of time between the physical world and the computational system. Many modern CPS, especially industrial automation systems, require the actions of different computational systems to be synchronized at much higher rates than is possible through ad hoc designs. Fundamental research is needed in synchronizing clocks of computing systems to a higher degree, and even if the clocks are synchronized, designing CPS nodes so that they can perform actions in a synchronized manner is challenging. We need to find ways to specify distributed CPS applications, ways to specify and verify timing requirements on distributed CPS, confident top-down design methodologies that can ensure the system meets its timing requirements in the first go, dynamically creating and dissolving timing domains using differently build components, and much more. In this talk, I will present some of the work that we have done, and some of the ideas that we want to pursue in order to solve the challenge of confident and simplified CPS design (from the timing perspective). We believe that confident CPS design is possible only when the timing requirements of CPS are specified in the application itself, and not as a separate document. It should not be a list of separate requirements, but must be married to the application specification in as natural way as possible. Second, we need techniques to design the CPS in one-shot. Provably correct by construction is very good, but even design methodologies that improve the confidence in design are also very important. Finally, there should be automated methods to test the CPS.
Keywords: CPS, Adhoc Network